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The IUP Journal of Electrical and Electronics Engineering:
A State-of-the-Art Review of Placement in FPGA.
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Any digital circuit can easily be implemented using Field Programmable Gate Array (FPGA) with accuracy and fast implementation rate. The quality of digital circuit depends on the placement technique. The placement technique determines the physical location of logic block on the FPGA. In this paper, a number of placement techniques are reviewed like min-cut, simulated annealing, analytical placer, evolutionary placer and hybrid approach. Each optimization technique is evaluated and the significant aspect of each technique is explained. An overview of the tools used in FPGA placement is also given.

 
 

Nowadays, all the modern electronic circuits are implemented using digital technique. As compared to Application Specific Integration Circuit (ASIC), Field Programmable Gate Array (FPGA) provides fast realization of digital circuits. FPGA has programmable components such as Configurable Logic Blocks (CLB), Switch Blocks (SB) and Input/Output Blocks (IOB). These programmable blocks can easily be programmed by a designer. Typical architecture of FPGA is shown in Figure 1.

A typical FPGA design process consists of logic synthesis, technology mapping, placement and routing. The logic synthesis is a process of minimizing the logic of circuit so that more and more logic can be loaded into limited area of FPGA. Technology mapping is the process of partitioning the optimized circuit such that each partitioned block is mapped onto the available logic elements in the FPGA. In the placement phase, these partitioned blocks are assigned to the specific cells of the FPGA layout. In the routing phase, horizontal and vertical channel are used to connect the placed logic blocks. The main object of the placement problem is to minimize the total placed area such that more and more logic can be added in the available FPGA area.

 
 
 

Electrical and Electronics Engineering Journal, FPGA, Placement placer, Simulated Annealing (SA), Genetic Algorithm (GA), Hybrid approach.