In Complementary Metal Oxide Semiconductor (CMOS) circuit designs, the low mobility (m_p) P-channel Metal Oxide Semiconductor (PMOS) devices are sized up to attain the same conduction performance as the high mobility (m_n) N-channel Metal Oxide Semiconductor (NMOS) devices. The PMOS/NMOS width ratio (b) is an important ratio in the design of digital circuits using conventional CMOS logic. The conventional method of estimating b excludes the effect of several technology parameters in estimation of PMOS/NMOS width ratio. This paper discusses a more accurate estimation of PMOS/NMOS width ratio, using relevant technology parameters like t_ox, V_tn, V_tp, Cj0n, Cj0p, Cj0swn, Cj0swp and built-in potential of PN junction (PB). b ratio is computed for 0.5 mm technology and compared to their values computed using the conventional method. The b ratio, taking into consideration many other technology parameters increases the inverter threshold (switching threshold) voltage V_th by 5% and average propagation delay by 0.6%.

In digital Very Large Scale Integration (VLSI) circuits, the conventional Complimentary Metal Oxide Semiconductor (CMOS) logic style offers robustness against voltage and transistor scaling and provides reliable operation at low voltages together with low switching activity, as compared to other logic styles. CMOS has high noise margins due to the presence of a static path that restores the correct logic state in the presence of noise. Logic gates in conventional CMOS are constructed from N and P blocks. The N block evaluates the `0' state, while the P block evaluates the `1' state, where only one of the blocks is conducting at a steady state. The main drawback of conventional CMOS circuits is the existence of the P block because of its low mobility (m_p) devices, compared to NMOS devices (m_n). Therefore, PMOS devices need to be sized up to attain the gate's performance. The highest noise margin for static CMOS is conventionally obtained by using a PMOS/NMOS width ratio (b) of m_n / m_p (Mohab et al., 2002; and Jan et al., 2004), which is also conventionally taken to provide identical current driving capability for the N and P networks. If symmetry and noise margin are not of prime concern, it is possible to speed up the inverter by reducing the width of PMOS device.

Conventionally, the best gate performance is supposed to be achieved with a PMOS/NMOS width ratio of (Mohab et al., 2002; and Jan et al., 2004), because, widening the P-channel Metal Oxide Semiconductor (PMOS) improves the t_PLH of the inverter but also degrades the t_PHL due to increased capacitance of the next stage. The above result is based on the assumption that ratio b depends only on mobility, while it actually depends on many other technology parameters. In this analysis, we have included the effect of relevant technology parameters in determining the ratio b. 0.5 mm technology has been considered for the present study. The explaination of the calculation of b and inverter threshold voltage (V_th) is followed by a description of dependence of b ratios on various technology parameters, a comparison of different b ratios for 0.5 mm technology, a comparison of inverter threshold voltage (V_th) for different b, a comparison of inverter average propagation delay for different b ratio, and the conclusion.

Comparison of Trans-Conductance Ratio (β) for a High-Speed Inverter Design, CMOS logic, Very Large Scale Integration (VLSI), Digital circuit design, Mobility, Technology parameters, threshold voltage, P-channel Metal Oxide Semiconductor (PMOS), voltage, transistor scaling.