The historical development of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) from the 1928 patent disclosures of the field effect concept and the semiconductor structures proposed by Lilienfield to the 1947 Shockley originated efforts led to the laboratory demonstration of the modern Silicon MOSFET 30 years later in 1960, leading to the emergence of sub-micron silicon logic Complementary MOS (CMOS) and bipolar CMOS arrays. The paper provides a brief overview of the challenges for further scaling of CMOS in nanometer regime for future Ultra Large Scale Integration (ULSI) technology in the light of fundamental physical effects and practical considerations with focus on important limitations. Thereafter, the paper explores the research and development of innovations beyond Si-CMOS towards new nanodevices based on distinctly different principles of physics with new techniques and four generations of nanotechnology development. Finally, it concludes with important perspectives for further CMOS scaling.

Today, CMOS technology has become the prevailing technology for Ultra Large Scale Integration (ULSI) applications to smaller dimensions for higher packing density, ultra low power dissipation and faster circuit speed. The steady-state downscaling of CMOS device dimensions has been the main stimulus to the growth of microelectronics and computer-aided future ULSI design [1]. The basic idea of scaling is to reduce the dimensions of the MOS transistors and the wire connecting them in the integrated circuit.

So, the arrangement on the right is scaled down in size from that on the left by reducing all dimensions by a factor `a'. Scaling achieves the same electric field patterns in the smaller transistors by reducing the applied voltage along with all key dimensions, including the size of the depletion region x_d; but the transistors can be turned off properly by the control gate [3]. The scaled down depletion regions allow the separation between source and drain (L) to be reduced along with the other physical dimensions. An interesting feature concerning especially the Silicon-On-Insulator (SOI) is that the silicon technology is becoming divorced from Bulk Silicon Material (BSM). Sub-10 nm gate length MOSFETs have been developed with a variety of structures. One of the smallest devices reported is a 5 nm using bulk silicon substrate [4, 5]. Nano and giga challenges in electronics and photonics [6] were launched as a truly interdisciplinary forum to bridge scientists and engineers to work across boundaries in the design of future information technologies, from atoms to materials to devices to system architecture.

CMOS Scaling, ULSI Technology, Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET, Semiconductor structures, Sub-micron silicon logic Complementary MOS, CMOS, Nanotechnology development, MOS transistors, Ultra Large Scale Integration applications, ULSI, Physical dimensions, Silicon-On-Insulator, SOI, Architectural innovations, Power management systems.