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The IUP Journal of Telecommunications
Evolution of Non-Conventional MOS Device Structures: A Review
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High packing density and low power dissipation in a chip are the needs of very large-scale integrated circuits. As technology is shrinking, conducting channels are becoming shorter to add more devices onto the fixed area, but simultaneously certain factors arise which degrade the device performance. To overcome the limitations of short channel MOS transistors, several designs for the device architecture like Double Gate (DG) and Triple Gate (TG) MOS structures have been explored. The paper reviews the performance advantages of each advanced structure and relative dependence on various process parameters. Also, the developed analytical models for calculating drain current, surface potential, transcapacitances, etc., of these structures have been assessed.

 
 

Several technical papers have been written since 1975 to examine the effects of scaling on the MOSFET device performance. As per ITRS specifications, technology node will reduce to 5 nm by the year 2020 (ITRS 2.0, http://www.itrs2.net). The increasing demand for more transistors per chip has resulted in scaling the dimensions of conventional MOS transistors. However, scaling contributes to several Short Channel Effects (SCEs), i.e. (i) velocity saturation; (ii) impact ionization; (iii) Drain Induced Barrier Lowering (DIBL); and (iv) hot electron effects (Pierret, 1996). To mitigate these effects, Ultra Thin Body (UTB) MOSFETs and multigate MOSFETs have been suggested (Chang et al., 2000 and 2003). But, nonalignment of gates in multigate MOSFETs can have serious impact on the device performance. A new structure in the form of in-shaped Field Effect Transistors (FinFETs), was developed, where gates are self-aligned and this DG device structure is comparatively easy to be fabricated; gate lengths in these structures can be downscaled to less than 10 nm (Hisamoto et al., 2000). Depending on the structure and number of active gates, FinFETs can be Double Gate (DG), Tri Gate (TG) or all around structure so as to improve gate control of the channel and minimize SCEs (Giacominia and Martino, 2008; Tawfik and Kursun, 2008; Zhang et al., 2012; Fasarakis et al., 2014; and Clarke, 2014).

 
 

Telecommunications Journal, Drain Induced Barrier Lowering (DIBL), FinFETs, Modeling, Short Channel Effects (SCEs), Subthreshold slope, Threshold voltage