The IUP Journal of Electrical and Electronics Engineering
Design of Low Power Full Adder Using Multilayer Perceptron to Minimize Energy Delay Product of Computational Logic Circuits

Article Details
Pub. Date : Apr, 2022
Product Name : The IUP Journal of Electrical and Electronics Engineering
Product Type : Article
Product Code : IJEEE30422
Author Name : C Pakkiraiah* and R V S Satyanarayana**
Availability : YES
Subject/Domain : Engineering
Download Format : PDF Format
No. of Pages : 17



In many arithmetic processors and digital signal processing applications, the binary adder is the primary computing block. Many electronic vendors have increased the demand for the least delay and minimum power consumption adders with multioperands to be consolidated in the present portable systems. In recent techniques, there has been a tendency regarding the expansion of programmable modules where processors utilize them to provide flexibility and execution. Mainly, neural network configurations are functionally verified by using software provinces. The utilization of the intended style of software implementation has many merits. The constraints of software perception of neural networks can be controlled using hardware implementation. The foremost interest of this paper is to realize the Exclusive-OR gate by Artificial Neural Network (ANN) using Multilayer Perceptron's (MLP) and activation functions as neuron output data values. The implementation results show that the MLP XOR and FA design attained notable refinement in contrast with the other described designs by achieving substantial savings in the total power dissipation and EDP.


Nowadays, modern real-time embedded systems are developed using digital logic design to encounter tradeoffs such as delay, power dissipation, cost and area. The low power design methodology was introduced by Pakkiraiah and Satyanarayana (2022). The realization of logic gates using Neural Networks (NNs) was presented by Ganesh and Prakash (2021). The nanoparticle computing architecture (Kim et al., 2020) was developed for nanoparticle NNs. NNs appear to be widely used in modern computer perceptron applications due to their improved forecasting capabilities. The concept of NNs was explained by exploring and designing logic gates and half-adder modules (Sabbaghi et al., 2019). The reconfigurable constant coefficient multipliers were demonstrated using NNs by Faraone et al. (2019). The paper inspects the implementation of NNs in Field Programmable Gate Array (FPGA) and determines the resource utilization


1-bit Adder, ANN, Dynamic power dissipation, EDP, MLP