| Pub. Date | : Apr, 2020 |
|---|---|
| Product Name | : The IUP Journal of Electrical and Electronics Engineering |
| Product Type | : Article |
| Product Code | : IJEEE20420 |
| Author Name | : Samayita Sarkar1, Rimi Ghosh, Bikash Dey, Juli Kumari |
| Availability | : YES |
| Subject/Domain | : Engineering |
| Download Format | : PDF Format |
| No. of Pages | : 6 |
Reducing the power consumption in VLSI circuits is a prime concern nowadays. Memory circuits play an important role in the design of electronic small power devices. Almost every digital system has memory as an important part in their design. The high speed circuits dissipate a considerable amount of power in a short time. In this paper, conventional SRAM cell is modified a little bit to reduce the dynamic power dissipation. The overall capacitance is reduced by adding a few extra transistors. Because of the fact that charging and discharging of the bit lines consume most power, 6T cell and 8T cell can be used to reduce the power by adding an extra number of transistors to the pull down path. 6T SRAM cell and 8T SRAM cells are simulated and their performance is compared in terms of power dissipation.
Low power and high performance are a challenge nowadays. There is an increasing demand for designing low power battery-operated portable devices, which would consume very little power. SRAM is an inherent part of most of the systems in the VLSI domain (Aly and Bayoumi, 2007; Keejong and Hamid, 2008; and Prashant and Rajesh, 2010). The speed and power consumption are important issues in designing the SRAM circuit (Martin, 1999). Conventional SRAM cell uses 6 transistors for both reading and writing operations. It has an advantage of less area (Takeda et al., 2006). Reading and writing are done through single bit line (Budhaditya and Sumana, 2011). The logic after writing is stable, but to read, there is a need for extra circuitry-like sense amplifier (Paridhi and Dasgupta, 2009). The existing 8T circuit proposed by Nahid and Singh (2013) is also simulated along with conventional 6T cell and transient analysis is done on the circuit, and also the power dissipation is calculated. The existing circuit uses 8 transistors. The central idea in 8T transistor is that the stored value inside the SRAM cell is sent through different transistors to get the read output. The paper concentrates on the design and simulation of conventional 6T SRAM cell and advanced 8T SRAM cell and compares the power dissipation for both the cells. Simulation and analysis are performed using a generic 250 nm model file. The results of power dissipation are compared between conventional 6T SRAM cell and 8T SRAM cell.
Power dissipation, SRAM cell, Power dissipation, tanner tools, VLSI