The IUP Journal of Electrical and Electronics Engineering
Greedy Simulated Annealing for FPGA Placement

Article Details
Pub. Date : Oct, 2019
Product Name : The IUP Journal of Electrical and Electronics Engineering
Product Type : Article
Product Code : IJEEE41910
Author Name : Jyoti Chugh
Availability : YES
Subject/Domain : Engineering
Download Format : PDF Format
No. of Pages : 09



VPR tool provides high quality solution for FPGA but takes large CPU placement time. Placement strategy in VPR tool is based on Simulated Annealing (SA) algorithm. The paper finds a method using which the CPU placement time can be reduced by adding short-term memory, which is called Greedy Simulated Annealing (GSA) algorithm. The experimental results show that it reduces 80% CPU placement time by paying 2% placement quality.


FPGA is flexible in nature. It can be programed and reprogramed very easily and quickly. This is the main advantage of FPGA. FPGA is programmed in six major steps: (1) logic synthesis; (2) technology mapping; (3) packing; (4) placement; (5) routing; and (6) bits stream generation. Maximum time is consumed by placement and routing phase (Shahookar et al., 1991). VPR tool using Simulated Annealing (SA) algorithm provides high quality solution with the expense of large computation time. VPR placer algorithm needs to be modified to provide high quality solution with a reasonable amount of time.


FPGA, Greedy Simulated Annealing (GSA), Placement placer, Simulated Annealing (SA)

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