Wireless technologies to support a gigabit data rate access point exploiting the potential of smart spectrum reuse have provided many more new wireless network services and applications than ever before. The next generation of general-purpose wireless LAN has introduced MIMO systems to the mass market by enabling the usage of many tiny timing differences in the paths between each transmitter/receiver combination through creating parallel channels. This strategy further offers scope to implement OFDM and provides a good solution to the ISI problems. Obviously, the appropriate usage of smart antenna in the adaptive beamforming techniques to implement space diversity, along with channel aggregation, encoding and signal conditioning strategies, has improved the channel bandwidth and power efficiency of the wireless systems significantly. Network researchers also focus on the innovation and improvement of the VLSI hardware to implement real-time digital signal processing by embedding the instructions and suitable software on the reconfigurable platform to implement the required multitasking.

The current issue consists of six papers: the first two papers address the wireless link improvement techniques based on single and multiple antenna systems, followed by the next four papers that discuss the issues of signal processing and VLSI hardware subsystem design and implementation used in wireless network system design.

The first paper, “Novel Multi-Slotted Stripline Fed Patch Antenna with Wideband Characteristics for Wireless Applications“, by P A Ambresh, A A Sujata, P M Hadalgi and P V Hunagund, proposes a new type of Multi-Slotted Patch Antenna with Stripline Fed (MSPASF) to show dual wideband characteristics with a better Return Loss (RL) up to –20 dB with a gain of 6.1 dBi. The paper also reports a significant enhancement in the impedance bandwidth by proposing novel slots in the patch plane.

In a wireless communication, a higher data rate transmission with minimum number of errors uses the MIMO techniques. The second paper, “Performance Analysis of 4 * 2 and 4 * 3 MIMO Systems Using MATLAB“, by Ritu and Kusum Dalal, focuses on MIMO techniques and considers two different MIMO systems for transmission and reception of the data to exploit the space diversity potential of such systems. The authors have used the Space Time Block Codes (STBC) for encoding the data to characterize the errors in data transmission.

The third paper, “Three-Dimensional Image Compression Using 2.5D Spatial Subsampling and Reconstruction Using 2.5D Morphological Filters”, Trupti Ahir and R V S Satyanarayana, describes a novel approach to compress a 3D image up to 25% and also reconstruct it with a high level of reliability. Spatial sparsing is used to subsample every slice of a given 3D image, and then slice-wise reconstruction is carried out using certain morphological filters. The error introduced by this compression technique is considerably small when compared to other techniques.

A logic circuit that is capable of converting the digital information in one form to another form is known as code converter. The code converters are essential in some digital systems such as microprocessors, micro controllers and DSP in order to perform various operations. The fourth paper, “Designs for Gray to Binary Code Converter Using Reversible Logic“, by Gowthami P, proposes a design for gray to binary code converter using reversible logic. The proposed design shows better performance in parameters such as gate count, constant inputs, quantum cost and garbage outputs than the existing designs.

A high speed digital signal processing hardware requires a multiplier to perform complex binary multiplication and thus needs better circuitry and algorithm to realize these components. The fifth paper, “A Comparative Analysis of Different Types of Multipliers“, by Monu Kumari and Sunita Malik, presents a comparative analysis of different types of multipliers like booth, array and Wallace tree multipliers based on different performance metrics mainly with a focus on reducing the partial product stages.

The last paper, “Design and Implementation of a 32-Bit ALU: A Review“, by Hari Nandan and Pawan Kumar Dahiya, is a review that discusses different techniques to design and implement a 32-bit Arithmetic and Logic Unit (ALU) for Digital Signal Processor (DSP) core, multifunctional processor and cryptographic processor designs.