Nowadays, wireless communication is the preferred mode to transmit information and hence it is required that the data is transmitted with minimum number of errors. For transmission of large amount of data at once, a technique named MIMO is used, but in this technique also, the data needs to be encoded in such a way that the probability of error at the receiver side is reduced. The paper focuses on MIMO technique and considers two systems, 4 * 2 and 4 * 3, for transmission and reception of the data. For encoding the data, Space Time Block Codes (STBC) scheme is used and a comparison is done to find out the better system for data transmission with minimum amount of error.

Three-dimensional image compression is an important requirement in 3D medical imaging applications. The paper describes a novel approach to compress a 3D image to 25% and reconstruct it so that the reconstructed image is almost close to the original image. Spatial sparsing is used to subsample every slice of a given 3D image, and slice-wise reconstruction is carried out using certain morphological filters. This technique is called 2.5D compression of 3D images.

In recent years, reversible logic has gained importance in several emerging fields such as nanotechnology, quantum computing, optical computing and cryptography. The paper proposes a design for gray to binary code converter using reversible logic. The proposed design shows better performance in parameters such as gate count, constant inputs, quantum cost and garbage outputs, than the existing designs.

The paper presents an analytical comparison of different types of multipliers like booth, array and wallace tree multipliers based on different performance metrics such as power, area and speed by reducing the partial products. Partial products are mainly responsible for complexity and area, so the paper focuses on reducing the partial product stage. It is found that wallace tree multiplier is best among all the above multipliers. As the multiplier size increases, the complexity also increases in wallace tree, so booth multiplier is best for large size.

The paper proposes different techniques to design and implement a 32-bit Arithmetic and Logic Unit (ALU) such as implementation of 32-bit ALU for Digital Signal Processor (DSP) processor core, multifunctional processor, cryptographic processor and Wi-Fi enabled 32-bit ALU, reversible gate, Feedback Switch Logic (FSL) and clock gating. The number of operations increases in ALU, due to which the complexity of operation increases and causes an increase in power consumption also. To reduce the power consumption in ALU, the paper designs the ALU with clock gating. All these designs are implemented on FPGA.