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The IUP Journal of Telecommunications

Implementation of Crosstalk Avoidance and Low Power Coding Scheme for SoC.

Article Details

Pub. Date	: Feb, 2018
Product Name	: The IUP Journal of Telecommunications
Product Type	: Article
Product Code	: IJTC41802
Author Name	: D Chakradhar and B Obulesu
Availability	: YES
Subject/Domain	: Science & Technology
Download Format	: PDF Format
No. of Pages	: 13

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Abstract

The paper proposes a coding scheme for avoiding crosstalk and reducing power consumption. System-on-Chip (SoC) buses are associated with delay, power and reliability problems. Capacitive crosstalk and high power consumption due to various capacitances are the major causes of this problem. Verilog simulation of encoder and decoder modules are designed to avoid these problems.

Description

System-on-Chip (soC) is defined as the fabrication of all the computer components on a single silicon chip (Pasricha and Dutt, 2008). This in turn reduces the development cycle and increases product functionality, performance and quality. Modems, mobile phones, DVD players, televisions and iPods are the examples of integration. Integration or fabrication of all components needs analog as well as digital circuits, processors and firmware, for example, single-chip mobile phone. The main advantages of single chip fabrication are low cost, decreased size and reduced power consumption. Due to long buses, a large amount of power is dissipated in digital circuits. The interconnect width and space reduction due to DSM technology in CMOS in turn increases the interwire capacitance and interconnect resistance.

The coupling capacitance is significant in deep submicron compared with the bulk capacitance. Hence, the wire delay becomes more due to capacitive crosstalk on adjacent wires. This delay is referred to as crosstalk delay; coding techniques have been proposed to avoid crosstalk delay.